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Heat up integrality: Number of IC of low power comsumption designs necessary tec
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Heat up integrality: Number of IC of low power comsumption designs necessary technology
On the design automation congress of this year, new old supplier is contended for roll out power to design a tool, aim to provide a kind of when evaluate power comsumption better means for digital IC stylist.

. The power comsumption of leak shows exponential growth along with temperature.
. On 90nm craft node, leak occupies the 25%~45% of total power comsumption. When 65nm craft, leak occupies 50%~70% of total power comsumption.
. Piece on temperature can affect sequential. Every raise temperature 15 ℃ , defer can increase make an appointment with 10%~15% .
. Increase as temperature, EM also can show exponential growth, make product life is reduced fourfold.
. Resistor and temperature show linear concern, meeting influence IR falls. The temperature change of 15 ℃ can make resistance increases 10% .
. Clock door accuses with aggravate of multi-line Cheng CMOS a change of quantity of heat that go up. Since going 3 years, the attention that chip stylist manages to IC power had jumped the first from the 3rd former, the stylist of the ASIC in applying to those portable systems especially and SoC, the case is more such. Then, the design automation plenary meeting that this year American California Anaheim held in June (DAC) on the first time appeared on a lot of power tools. Experts say, if want to control transistor leak truly (the proportion that this kind of leak holds systematic power comsumption is larger and larger) , with respect to the fuel factor that must understand oneself to design first, and the influence of sequential of IC of their logarithm word and dependability. Experts claim, once mathematical calculation gave the calorific amount of chip, can make oneself design utmost ground has correct power comsumption, function and reliability.

If you are using the geometrical dimension of 90nm or 130nm craft to undertake designing, managing with respect to power of can clear IC is a big question. Company of a few EDA developed a few estimation the tool of effective power comsumption, effective power comsumption is the energy that the system that gives through move normally and be being calculated wastes. Some suppliers also had developed the tool that tries to show leak power, this is the system is in bide one's time the power of leak of the transistor when mode. Leak is a problem when 0.13mm craft, enter all the more when 90nm and 65nm craft when the design serious. Experts think, without accurate hot analysis, stylist cannot consider leak problem and IC power comsumption.

Apache designs plan company president to hold CEO Andrew Yang concurrently to say: "Rise as temperature, leak can show an index to increase. TSMC (the stage accumulates report) the company is conjectural, leak should consume the general power of 50% . We had asked this question to the client that realizes a design with 90 Nm silicon chip, their answer is the power that leak wants to use up 25% ~ 40% . When turning to 65 Nm, we reckon the general power that has 50% ~ 70% passes leak and dissipation is dropped. " a lot of leak results are created by inaccurate temperature estimation, and great majority is not accurate because was used,be convey to enclose the out of date that reachs systematic stylist highest temperature limitation and model be caused by.
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